Industry: Networking / Datacenter Hardware — High-speed multilayer PCB design at up to 1.6 Tbps backplane class.
Objective
High-speed networking hardware is one of the few electronics domains where every fractional improvement in signal integrity is measured against the millions of dollars that downstream traffic engineering can extract per percentage point of link reliability. At backplane data rates approaching 1.6 Tbps, the PCB is not a passive substrate — it is a deliberately tuned transmission environment, and every via, every length mismatch, every dielectric choice is part of the signal-conditioning chain.
The Challenge
Our client engagement was a multi-layer high-speed PCB design contribution focused on DDR memory interfaces, Ethernet at the highest tier of the standard, and the kind of integrated PCIe and processor subsystems that anchor modern networking and datacenter hardware. The board had to support DDR routing within timing budget, Ethernet differential pairs at the high-bandwidth tier with controlled impedance and minimal skew, and the kind of stackup decisions that hold up across the impedance variations a real fabrication shop introduces.
The work spanned full-cycle PCB design — schematic interpretation, stackup definition, layout, SI/PI review, fabrication and assembly readiness — for boards operating at the leading edge of the high-speed networking envelope.
Why It Required Specialist Engineering
At these data rates, PCB design becomes a discipline where the design rules you can articulate are less than half of what determines whether the board works. The intuition you bring from many earlier high-speed designs, the reviews you do that catch things the rules do not enforce, the fabrication relationships that let you trust the stackup you specified — those are the things that distinguish a board that hits its target spec from a board that has to be re-spun.
Engineering insight
At 1.6 Tbps, the PCB IS the design. The signal-conditioning chain runs through the copper, not around it.
Milestones
The engagement covered PCB design, layout review, manufacturing readiness, and signal-integrity optimization across the lifecycle.
High-Speed PCB Design
- Contributed to high-speed PCB design including DDR3 and DDR4 memory interfaces and Ethernet at the highest data rates the standard supports.
- Worked on systems with effective backplane data rates up to 1.6 Tbps, where impedance control, length matching, and routing topology are not constraints — they are the design.
- Designed stackups optimized for the dielectric and impedance behavior the high-speed interfaces required, with careful planning of layer assignments for differential pairs, controlled-impedance routing, and dedicated planes.
- Implemented HDI techniques, fine-pitch BGA routing, and blind/buried/microvia structures where the high-density interconnect requirements demanded.
Impedance Control and Signal-Integrity Reviews
- Performed layout reviews focused on impedance control and signal/power integrity (SI/PI), with attention to the practical questions a fabrication shop will need to answer to actually build the board reliably.
- Reviewed differential pair routing for length matching, via-stub minimization, and the kind of return-path discipline that determines whether a high-speed interface meets its eye-mask budget across temperature and supply corners.
- Conducted SI/PI co-design across the high-speed interfaces and the surrounding power-delivery network, recognizing that signal integrity at these data rates is inseparable from power-delivery quality.
Manufacturing Readiness and Design Optimization
- Supported manufacturing readiness across the design, including fabrication and assembly review with PCB vendors, ECO support during board revisions, and the kind of cross-team coordination that ensures the design that reaches the assembler is the design that was simulated.
- Generated and reviewed release packages including Gerber, ODB++, IPC-2581, fabrication drawings, and assembly drawings, with attention to the documentation precision a high-speed board requires.
- Participated in DFM reviews with PCB fabrication and assembly vendors, surfacing the stackup-level and via-level decisions that affect manufacturability and yield.
Cross-Functional Collaboration
- Collaborated with hardware, SI, PI, and manufacturing teams throughout the product lifecycle, treating the boundaries between disciplines as the place where the most-valuable engineering decisions get made.
- Supported ECO implementation and PCB revision control activities, with the documentation discipline that lets a design get to revision N without losing fidelity from revision 0.
Outcome
What Was Delivered
Manufacturable high-speed boards passing SI/PI validation and ready for production transfer, contributing to platforms operating at the leading edge of the networking and datacenter data-rate envelope. The design contributions held up across the kinds of fabrication and assembly variability real manufacturing introduces, with the layout decisions made early in the program supporting the validation results achieved later.
Engineering Quality
Layout review discipline caught the kinds of issues that would have surfaced as eye-mask failures in lab characterization, allowing them to be resolved at the design stage rather than after fabrication. Stackup decisions were made in coordination with the fabrication partner, so the impedance assumptions in the layout matched the impedance behavior of the manufactured board. SI/PI co-design produced boards where the power-delivery network supported the signal-integrity envelope the high-speed interfaces required.
A pattern we see in high-speed design
At backplane data rates above the gigabit threshold, the boards that work are the ones where the PCB engineer was treated as a peer of the SI/PI specialist and the silicon designer. The boards that don’t work are the ones where they were sequenced.
Why This Matters
For the client, the outcome was high-speed boards that hit their data-rate and reliability targets without the multi-spin debug cycles that define a less-disciplined design process. For us, the engagement was a representative example of high-speed PCB design at the upper edge of the standard: where every routing decision, every via choice, every stackup specification compounds into the eye-mask margin that determines whether the board ships.
The engagement also illustrated the value of integrated SI/PI/PCB thinking at the highest data rates. Specialists who can only see their own discipline produce boards that pass each individual review and fail the integrated validation. Specialists who can hold all three in mind simultaneously produce boards that work.
Technologies
High-speed interfaces: DDR3, DDR4, multi-tier Ethernet (up to 800 Gbps and 1.6 Tbps backplane class), PCIe, processor-centric high-speed subsystems. PCB stackup and layout: controlled-impedance routing, length-matched differential pairs, via-stub minimization, dedicated power and ground planes, HDI techniques, fine-pitch BGA routing, blind/buried/microvias. Release packages: Gerber, ODB++, IPC-2581, fabrication and assembly drawings. SI/PI analysis: signal-integrity simulation and review, power-integrity co-design, decoupling network optimization. Tools: Cadence Allegro PCB Designer, Constraint Manager, Ansys SIwave, Ansys HFSS.
Services
High-speed multilayer PCB design · DDR and Ethernet interface implementation · Stackup and impedance design · Length matching and routing topology · SI/PI co-design and review · HDI and fine-pitch BGA routing · Manufacturing readiness · Fabrication and assembly coordination · ECO implementation · Cross-functional engineering coordination