When Does Signal Integrity Matter?
Signal integrity (SI) becomes a design concern when trace length exceeds roughly one-tenth of the signal wavelength in the PCB medium. For a signal with a 1 ns rise time on FR-4, this critical length is approximately 0.7 inches (18 mm). Beyond this length, the trace behaves as a transmission line, and reflections from impedance mismatches cause signal degradation.
Controlled Impedance Design
Controlled impedance requires matching the PCB stackup geometry to target impedance values. Common targets include 50 Ω single-ended for general high-speed signals, 90 Ω or 100 Ω differential for USB, HDMI, and Ethernet, and 85 Ω differential for PCIe. The trace width, dielectric thickness, and dielectric constant determine the characteristic impedance. Fabricators typically guarantee ±10% impedance tolerance with proper stackup specification.
Termination Strategies
Series Termination
A resistor placed near the driver matches the driver output impedance plus the resistor to the line impedance. This is the most common strategy for point-to-point connections. The resistor value equals Z₀ minus the driver output impedance.
Parallel Termination
A resistor to ground (or to a termination voltage) at the receiver end absorbs the signal energy, preventing reflections. Used for bus architectures and multi-drop configurations. Consumes DC power continuously.
AC (RC) Termination
A series RC network at the receiver provides frequency-dependent termination without DC power consumption. The capacitor blocks DC while the resistor terminates high-frequency components. Common values: 33 Ω + 33 pF.
Practical Guidelines
- Route high-speed signals over continuous reference planes
- Minimize via count in critical signal paths
- Match lengths for differential pairs to within 5 mils
- Keep stub lengths below λ/20 at the signal bandwidth
- Use ground vias near signal vias to maintain return path continuity
Our PCB design team specializes in impedance-controlled layouts for high-speed digital and RF applications. We perform pre-layout SI analysis and post-layout verification to ensure signal quality. Contact us for expert high-speed design support.